One of the most useful electronic circuits is one that generates a digital (a periodic on-off) signal for controlling the operation of one or more digital or digitally controllable devices. It is most useful when the ratio of the on-time during each cycle to the off-time of the cycle, that is, the duty cycle ratio, can be easily varied and controlled. In some embodiments of the basic controller circuit, the linear variance of an analog device, that might for example provide an adjustable voltage, current, or resistance in the circuit, is translated into a linear variation in the duty cycle ratio of the output digital signal.
A number of different types of digitally based duty cycle controllers are known in the art, and may include a modulo-N counter-timer in cascade with a modulo-M counter-timer, where N+M is held constant and defines the output clock frequency, while the period of an input reference clock determines the resolution. Another method employs a shift register having a series of fixed delay interval stages with interposed user selectable taps. According to this method, the output delay or duty cycle ratio is established in discrete steps that depend on the tap selected and on the fixed time delay contributed by each of the internal delay stages.
Normally, the propagation delay of a simple digital gate (or flip-flop) defines the duty cycle adjustment granularity, that is, the shortest incremental delay step achievable. U.S. Pat. No. 5,682,114 issued to Ohta, however, teaches another time delay control technique wherein the differences between the charging time constants of MOSFET gate capacitances provide a relatively shorter single stage delay. Furthermore, each single stage delay can be directly varied by digitally controlling how many MOSFET gate capacitances are connected in parallel at each delay node. Multiple stages can be cascaded for longer delays.
A similar technique for producing short selectable delay intervals is taught in U.S. Pat. No. 5,933,039 issued to Hui et al., wherein the delay at each node is fine-tuned during manufacture. Each nodal capacitance is held constant while the effective nodal charging current is adjusted to properly calibrate each of the individual time delay steps. To achieve longer delay periods, these stages may be concatenated as needed under user programming control.
The basic output element of most analog time delay designs constitutes a detector whose output changes state when a time varying input voltage crosses its input switching threshold. A current source, or a voltage source driving a resistor serving as a voltage-to-current converter, connected to a capacitor generates a time varying voltage that may serve as the input to the detector. Initially, the voltage across the capacitor may be set to a known value to force the detector output into a given state s0. At a particular time, known as the trigger point, current is allowed to flow into the capacitor causing its the voltage to rise until a threshold voltage is reached whereupon the detector output switches to state s1. The time elapsed between these two events is determined by four analog circuit parameters: capacitance, initial capacitor voltage, charging current and detector input switching threshold voltage. If a reset mechanism for the capacitor voltage is provided, this circuit becomes formally equivalent to a retriggerable monostable multivibrator, similar to the well known 555 timer. In principle any one or more of these analog timing parameters can be varied to change the length of the time delay.
The simplest pulse width controller consists of a dual input AND gate, whose inputs exhibit substantially constant and equal switching threshold points, configured with one input being driven directly by the external clock while the other is connected to an RC low pass filter circuit driven by the same external clock; in this case, the voltage developed across the capacitor follows an exponentially decaying curve. With the inputs connected in this manner, the output can assume a logic high value only when the voltages of both the master clock as well as the output of the RC network exceed the gate's input switching threshold, so the duty cycle exhibited at the output of the gate will be determined by the delay due to the low pass filtering action of the RC network. Should the values of either passive element be variable in response to a suitable control signal, then adjustable time delay could be achieved.
Another common technique for analog time delay control is based on the use of an adjustable current source to produce a linear ramping capacitor voltage, with the other three timing parameters identified earlier being held constant. For example, an enhancement recommended for the 555 timer specifies the use of a simple transistor constant current source to linearize the capacitor charging current. Unfortunately, this is only useful for pulse widths down to tenths of a microsecond. In U.S. Pat. No. 4,843,255 issued to Steubing, a design for a fast (500 MHz), step-wise adjustable monostable multivibrator is disclosed wherein the charging current for the timing capacitor is the controlled parameter. By using a voltage controlled current sink to discharge a timing capacitor that has been preset to a known voltage, an accurate time delay is produced at the output of a suitable detector means. The current sink node is the collector terminal of a single common base transistor configured so that a voltage may be impressed across its emitter resistor by a precision DAC. The output of the DAC is connected to provide a relatively negative voltage with respect to the emitter, drawing a current out of the emitter resistor that is substantially equal to the sink current flowing into the collector. Base current compensation is also provided to improve performance.
A continuously variable monostable design, employing a ramp generator consisting of an adjustable current controlled current source and a fixed capacitor, is disclosed in U.S. Pat. No. 5,410,191 issued to Miura, where it appears as an embedded circuit within an FM demodulator. A more sophisticated compound technique to achieve precise timing over relatively long time periods is taught in U.S. Pat. No. 5,124,597 issued to Steubing et al., where the ramp type delay generator described in Steubing (255) is placed in cascade with a series of high speed timer-counter sections. The ramp delay means provides small step-wise vernier delay increments to the primary delay set by a number of cascaded counter-timer stages.
All of the methods described above are examples of open-loop pulse width and timing generators, that could in principle be used as part of a duty cycle controller. However, in every open-loop method, both accuracy and stability are dependent on the absolute values of internal analog quantities such as ramp timing capacitance and nodal charging currents. A significant level of precision can be achieved, but only at the expense of relatively complex circuitry.
On the other hand, a considerable increase in performance can be immediately realized by enclosing a basic retriggerable pulse width modulator within a high gain feedback loop that provides continual correction to the duty cycle ratio of an output clock signal, forcing it to track the value of an input control signal. Because of the fundamental difference in form between the controlling input (an analog voltage or current) and output (a stream of digital pulses), the feedback arrangement takes the form of a servo control loop. An output clock signal that exhibits the duty cycle ratio that is desirably controlled is fed back into the circuitry, where it is filtered to yield an averaged voltage proportional to duty cycle; this filtered voltage constitutes a feedback signal. The difference between this feedback signal and the input control voltage represents the loop error, which serves as the input to a very high gain amplifier configured as an integrator. The integrator, in conjunction with additional circuitry, operates in known fashion within a negative feedback loop to minimize the magnitude of the error signal by forcing the output duty cycle to accurately track the value of the input control signal.
The use of a servo integrator to establish proper time relationships between output signal waveforms was taught by the present inventor in U.S. Pat. No. 4,890,065 issued to Laletin. According to the disclosed technique, an unintentional inter-channel time delay between two related audio input signals is detected and corrected. A time delay between the inputs is determined by at least one analog cross-correlator so that the differential delay is suitably transformed to appear as an error voltage. A high gain amplifier, configured as a servo integrator, receives this error signal and provides control to a pair of voltage controlled time delay networks, each capable of introducing additional delay in their respective audio signal paths. These networks operate differentially under control of the servo integrator to force the inter-channel time delay to be linearly proportional to a controlling voltage signal, usually set to zero. However, using a non-zero control voltage can also effect a constant inter-channel time delay.
Another example of a fixed ratio duty cycle controller that relies on servo feedback is provided in U.S. Pat. No. 5,315,164 issued to Broughton, wherein the output duty cycle of a fixed frequency clock is determined solely by the ratio of two precision resistors embedded within the feedback circuitry. In this case, however, no provision is made for an external duty cycle ratio control input.
McEwan discloses two other examples of the use of a servo integrator to establish precise, adjustable timing relationships in U.S. Pat. No. 5,563,605 and No. 6,055,287. In each disclosure, a high gain amplifier configured as a servo integrator forces the duty cycle of an output clock signal to track a step-wise adjustable reference signal supplied by a DAC. The disclosed circuits employ several (more than three) digital elements, all of which toggle at the reference clock frequency leading to substantial current consumption at higher (>1 MHz) clock frequencies. CMOS logic gates are used as a fixed threshold detectors, each providing an adjustable duty cycle output clock. Instead of linearly varying the ramp slope or the detector threshold, the time delay is achieved by altering the DC bias of a low pass filtered version of the input reference clock that is then presented to the input of the CMOS detector. The edges of the filtered square wave signal exhibit an exponentially decaying shape, so as the filtered waveform is shifted up or down in response to the voltage output signal from the servo integrator, the point in time where each edge of the curved waveform crosses the fixed input threshold of the detector is varied, yielding more or less delay with respect to the edges of the reference clock input signal. Thus, an exponentially decaying waveform edge replaces the linear timing ramp seen in other designs. In principle, the high gain of the servo integrator should ensure that the overall transfer function relating the control input to the output duty cycle remains linear despite the exponential shape of the ‘timing ramp’. To achieve significant delays, however, a shallower wave front is required, necessitating more low pass filtering. Such additional filtering also reduces the overall amplitude of the low pass filtered waveform that is presented to the detector as a timing signal; for applications wherein significantly more delay may be required, the amount of filtering required would inevitably yield a waveform too small for reliable detection. For this reason, only a limited amount of delay, about 100 nsec, is actually achievable with this design.
A more elegant servo controlled duty cycle controller is disclosed by Chou, U.S. Pat. No. 6,060,922. A single MOSFET transistor serves as a controlled current source to provide charging current to the intrinsic capacitance of a circuit node. By periodically resetting the nodal capacitance voltage to ground in response to one edge of an external clock signal, a periodically repeating ramping waveform is produced that serves as the input to a logic gate acting as a threshold detector. A feedback arrangement is disclosed to force the averaged duty cycle voltage to be substantially equal to an externally applied reference voltage. An integrator sensing the output waveform directly drives one input of an open-loop operational amplifier while the other amplifier input receives the reference voltage signal. The dominant pole of the very high gain operational amplifier will add to that of the integrator (which itself has very high gain at low frequencies), leading to a potentially unstable system, especially for wide duty cycle ratios at lower clock frequencies. Furthermore, the equivalent input noise of the open loop operational amplifier is not suppressed by any local feedback, and will lead to excessive noise at its output with correspondingly increased timing jitter in the duty cycle ratio. Finally, whenever the input control voltage signal descends to a value corresponding to a sub-minimum pulse width (i.e., requiring a duty cycle having a positive pulse duration less than the sum of the reset time for the capacitor plus the time required for the capacitor's voltage to slew from ground to the detector threshold level), the output of the open loop operational amplifier will saturate at ground, leading to severely non-linear duty cycle performance during the early part of the ramp as a result of the protracted recovery period.
From the above, it is clear that a precision duty cycle controller embodying a voltage controlled, continuously variable pulse width modulator that avoids the shortcomings of previously disclosed designs, and that is stable for a wide range of frequencies and duty cycle ratios, is desirable. It would be especially useful if such a controller could be constructed without requiring either substantial operating current or an excessive number of logic elements operating at a high frequency, and without a plurality of amplifiers that have offset voltage and drift errors which, as a result of their arrangement within the circuit, cannot be corrected by overall loop feedback.